Responsibilities
- Develop testbenches and tests for our FPGA platform using an open-source, highly flexible environment
- Write detailed verification plans
- Efficiently root-cause RTL bugs
- Collaborate directly with designers to bring up new projects quickly and debug existing designs
- Manage regression and continuous integration infrastructure
- Enhance and develop open-source and internal tools
Qualifications
- Exceptional debugging and analytical skills
- Over 4 years of experience in RTL functional verification for FPGA or ASIC
- Proficient in code and functional coverage collection/analysis
- Experience with Python programming
- Comfortable working in a Linux environment
- Preferred familiarity with Verilator and/or Cocotb
- Preferred experience with networking protocols
- C++ experience is advantageous
- Bachelor's degree in Computer or Electrical Engineering or a related field
